Nvidia Built a 37-Member AI Security Alliance. OpenAI, Google, and Anthropic Didn't Show Up.
A 25-year-old founder's London startup is using light instead of electricity to deliver 10,000+ tokens per second per user — and has convinced Arm, Reed Hastings, and the UK government it can challenge Nvidia's inference economics.
On August 3, 2026, a 25-year-old founder's London startup raised $312 million at a $3.3 billion valuation to build AI chips that use light instead of electricity — and eliminated the expensive, supply-constrained memory component that accounts for a significant fraction of Nvidia's data center GPU cost.
The company is OLIX. The chip is the DX-1. The technology is called an Optical Tensor Processing Unit, or OTPU. The investors who backed this round — Arm, Hudson River Trading, Reed Hastings (Netflix co-founder), and the UK government's Sovereign AI Fund — are not naive capital chasing AI hype. They are betting on a fundamentally different physics of computation reaching commercial scale in 2027.
Understanding why requires understanding what OLIX is actually solving, and why the bottleneck it is targeting is the right one to attack.
The HBM Problem Nobody Talks About at the Marketing Layer
High-bandwidth memory is the unheralded constraint at the center of the AI infrastructure crisis.
Every Nvidia H100 and H200 GPU carries between 80GB and 141GB of HBM — memory stacked vertically in layers of DRAM, bonded to the GPU die, that can transfer data to the compute core at rates measured in terabytes per second. HBM exists because large language models are bandwidth-constrained, not compute-constrained: the bottleneck in LLM inference is not the speed of the matrix multiplications but the speed of moving the billions of parameters that define the model from memory to the compute units that process each token.
HBM solves this by shortening the physical distance between memory and compute, achieving bandwidth that conventional DRAM — located on separate chips connected by printed circuit board traces — cannot match. But HBM creates three compounding problems:
Cost. HBM stacks are manufactured by two companies — SK Hynix and Micron — in a process that is substantially more complex and expensive than commodity DRAM. Each HBM stack in an H100 GPU adds several thousand dollars to the bill of materials. SK Hynix's recent Nasdaq IPO was positioned explicitly as an HBM supercycle play — which tells you that the demand is extraordinary but so is the pricing power of the suppliers.
Supply. HBM manufacturing capacity cannot be quickly expanded. The specialized equipment required — thermocompression bonding tools, advanced packaging lines — has lead times measured in years. When AI infrastructure buildout surged in 2024 and 2025, HBM supply constraints became a binding limit on GPU production and the primary reason Nvidia H100 lead times extended to six months or longer.
Physics. HBM achieves its bandwidth by shortening the electrical path between memory and compute. But electrical signals traveling even short distances consume power proportional to the capacitance they must charge and discharge, and they generate heat. The aggregate power consumption of HBM bandwidth at the scale of a large inference cluster is significant — and this power consumption does not scale away with process node improvements, because it is a function of the physics of moving electrical charge, not the density of transistors.
OLIX's approach attacks all three problems by eliminating HBM from the inference compute path. The DX-1 uses on-chip SRAM — conventional static RAM that can be integrated at high density on a photonic chip — to store model weights locally, reducing the data movement bottleneck by keeping weights close to compute. The photonic compute core then performs the matrix multiply operations using light propagating through optical waveguides rather than electrons moving through silicon transistors.
What Photonic Computing Actually Means
Photons do not behave like electrons. This matters enormously for computing.
Electrons have mass, charge, and interact with the electromagnetic fields of other charges around them. When an electrical signal travels through a wire or transistor, it charges and discharges capacitance, dissipates energy as heat, and is limited in speed by the resistance and capacitance of the conducting path. Silicon transistors operate by controlling the flow of electrons through a channel — and as transistors shrink to below 3 nanometers, quantum effects make this control increasingly difficult. The era of scaling through transistor miniaturization is reaching physical limits that process engineers cannot engineer away.
Photons have no mass, no charge, and do not interact with each other. Light propagating through an optical waveguide does not heat the waveguide, does not dissipate energy through resistive loss, and can carry information at the speed of light. Multiple wavelengths of light can propagate through the same waveguide simultaneously without interfering — a property called wavelength division multiplexing that has been used in fiber optic telecommunications for decades to achieve enormous bandwidth in a single fiber.
For AI inference, the relevant operation is the matrix-vector multiply-accumulate: multiply a vector of activations by a matrix of model weights and sum the results. In silicon, this is performed by an array of multiply-accumulate units consuming electrical signals. In OLIX's OTPU, an equivalent operation is performed optically: the weights are encoded as optical attenuations, the activations as light intensities, and the multiplication and summation happen as light propagates through the optical network, consuming energy only at the input (where the light is generated) and output (where it is detected), not in the computation itself.
The result is computation that is inherently more energy-efficient at the physics layer — independent of whether a semiconductor process node is 3nm or 1nm. This is the structural long-term advantage that photonic computing offers: it does not depend on transistor scaling, so it does not inherit the limits that transistor scaling is approaching.
The DX-1 and the Decode Bottleneck
OLIX's DX-1 chip targets a specific phase of LLM inference: the decode stage.
LLM inference has two distinct computational phases. The prefill phase processes the input prompt — it is compute-intensive and benefits from GPU parallelism. The decode phase generates the output tokens, one at a time — it is memory-bandwidth-intensive and is where production inference systems spend most of their time.
| Inference phase | Primary bottleneck | GPU efficiency | OTPU opportunity |
|---|---|---|---|
| Prefill | Compute throughput | High | Lower relative advantage |
| Decode | Memory bandwidth | Low (sequential) | High — SRAM weight access |
| KV cache management | Memory capacity | Moderate | Benefits from SRAM density |
| Batching | Throughput × latency | Variable | High at high concurrency |
The decode phase is memory-bandwidth-limited because the model must load the full weight tensor for each layer from memory into compute for every token generated. A 70 billion parameter model has approximately 140GB of weights at BFloat16 precision — weights that must be accessed in full for every output token, regardless of how many tokens of context have already been processed. At 10 tokens per second per user, the memory bandwidth required scales linearly with concurrent users.
GPUs address this by batching many users' decode passes together, amortizing the weight-loading cost across a large batch. But batching introduces latency — you must wait for enough users' requests to accumulate to fill a batch before processing begins. For interactive applications where latency matters (customer service, code completion, real-time agents), this batching trade-off is a genuine product constraint.
OLIX's DX-1 claims to deliver over 10,000 tokens per second per user precisely because the optical compute path does not pay the memory-bandwidth tax in the same way that electronic GPU decode does. With weights stored in on-chip SRAM rather than HBM, and with matrix multiplications performed optically rather than electronically, the DX-1 can achieve high token throughput per user at lower latency than batched GPU inference — the combination that enterprise interactive AI applications actually need.
The Funding Signal: Who and Why
The investors in OLIX's Series B are not a random collection of AI enthusiasts. Each participant has a specific strategic reason for backing a photonic AI inference chip.
Arm designs the processor instruction set architectures used in the vast majority of mobile and a growing share of data center chips. Arm's participation in an OTPU investment signals one of two things: either Arm is hedging against a future where photonic accelerators require different processor control logic, or Arm is actively planning architectural integration between its CPU designs and OLIX's OTPU for the co-designed compute systems that hyperscalers increasingly deploy. Either way, Arm's participation is a technical endorsement from the organization that understands chip architecture better than almost any other.
Hudson River Trading is one of the world's most sophisticated quantitative trading firms, with AI and machine learning at the center of its operations. HRT is an inference customer — it runs latency-sensitive AI models at high throughput and high concurrency. Its investment in OLIX reads as a strategic bet by a power user of AI inference infrastructure that photonic chips will deliver the latency and throughput economics that current GPU infrastructure cannot.
Reed Hastings turned Netflix from a DVD-by-mail business into a streaming platform by correctly betting on infrastructure economics at scale — specifically, that the cost of streaming bandwidth would fall faster than competitors expected. His participation in OLIX suggests he sees a similar infrastructure economics inflection in AI inference compute.
The UK Sovereign AI Fund represents the UK government's assessment that domestic photonic AI chip manufacturing is a strategic national asset worth £500 million in dedicated capital. The comparison to the relationship between TSMC and the Taiwanese government is instructive: semiconductor manufacturing has been recognized globally as critical national infrastructure, and countries that lack domestic capacity are recognizing the geopolitical and economic risk of dependence on foreign-controlled supply chains.
The Competitive Landscape: Where Photonics Fits
OLIX is not the only company building AI inference chips that challenge Nvidia's GPU. The landscape has several distinct approaches:
Etched built transformer-specific ASICs — chips with the transformer architecture hardwired in silicon, achieving extremely high throughput for transformer-based LLMs at the cost of model architecture flexibility. Etched's chips cannot be reprogrammed to run different model architectures; they are optimized exclusively for transformers.
Cerebras built the Wafer Scale Engine, the largest processor ever manufactured — a single chip the size of an entire silicon wafer, eliminating the chip-to-chip interconnect latency that limits GPU cluster performance on large models. Cerebras has shipped working hardware and has public customer deployments.
SambaNova and Graphcore built specialized AI accelerators using conventional silicon processes, targeting the gap between GPU flexibility and ASIC performance.
OLIX is distinct from all of these because its bet is at the substrate level — it is not optimizing how electrons flow through silicon but replacing electrons with photons for the core compute operation. This is a longer development path and a higher technology risk than silicon optimization, but it has a different ceiling: if photonic computing achieves commercial manufacturing maturity, it escapes the physics limits that constrain all silicon-based approaches.
How to Evaluate Photonic AI Chip Claims
Investors and enterprise buyers evaluating photonic AI inference claims should apply a structured framework:
1. Tokens per second per watt — normalize to efficiency, not throughput. Raw token throughput is easy to engineer by throwing more compute at a problem. The unit economics of inference that matter are tokens per second per watt and tokens per dollar of hardware amortized at reasonable utilization rates. Ask vendors to provide these numbers at specific utilization levels and model sizes.
2. Yield and manufacturing readiness — silicon has decades of process maturity. Photonic chip manufacturing is less mature than silicon CMOS. Yield rates (the fraction of chips produced that meet spec) directly determine per-unit cost. A chip that achieves impressive benchmark numbers at 10% yield is expensive; the same chip at 90% yield is competitive. Ask for independent yield data, not just benchmark data.
3. Software ecosystem — the CUDA lesson. Nvidia's CUDA lock-in is not primarily a hardware moat — it is a software moat built over 15 years of developer tooling, framework integrations, and optimized libraries. Any new compute substrate must be programmable with tools that AI developers already use (PyTorch, JAX, TensorFlow) or it will face years of ecosystem bootstrap before reaching production utility. Ask what OLIX's developer toolchain looks like and which frameworks it supports natively.
4. Deployment model — cloud, colocated, or on-premises. Photonic chips may have different thermal and form factor requirements than GPU racks. Understand what data center infrastructure photonic deployment requires and whether it is compatible with enterprise procurement and facilities management.
5. Transition cost — what happens to existing AI software stacks. A company running AI workloads on GPU infrastructure has invested in CUDA kernels, GPU-optimized batching logic, and GPU-aware serving infrastructure. The cost of migrating to a new compute substrate is not just hardware procurement but re-optimization of the software stack. Buyers should model total migration cost, not just hardware unit economics.
The Market Sizing and the 2035 Projection
The photonic AI chip market is valued at $3.14 billion in 2026 and projected to reach $20 billion by 2035 — roughly a 20% compound annual growth rate across a decade. For context, the total AI semiconductor market is currently estimated at over $150 billion annually, with Nvidia commanding roughly 80% of the AI accelerator portion.
A $20 billion photonic AI chip market by 2035 would represent roughly 10-15% penetration of the total AI accelerator market at its projected 2035 scale — a meaningful position but not a displacement of silicon-based computing. The more plausible scenario is that photonic computing captures specific inference use cases where its efficiency advantages are most pronounced: high-concurrency, latency-sensitive interactive AI applications where token-per-second-per-user performance is the binding constraint.
For the AI agent unit economics market — where agents must maintain persistent context, take real-time actions, and respond to users with sub-second latency — the economics of photonic inference are particularly attractive. An agent platform that can deliver 10,000 tokens per second per user at datacenter scale changes the unit economics of agentic product design.
What This Means for Enterprise Buyers and Infrastructure Decision-Makers
Enterprise AI infrastructure buyers are not choosing between GPU and OTPU today. OLIX's first commercial shipments are H2 2027, and the initial production volumes will be allocated to early strategic customers — likely hyperscalers and large model providers with enough inference workload to make photonic deployment economics work.
But infrastructure strategy decisions made today have 3-5 year horizons. The AI inference cost curve and compound pricing problem has been breaking faster than predictions, and inference that costs X today may cost 0.1X in three years — not because GPU prices fell, but because new compute substrates with fundamentally different economics reached commercial scale.
Enterprise buyers should be watching OLIX's H2 2027 first deliveries as a leading indicator of when photonic inference becomes a real procurement option. The questions to ask in the interim:
- What fraction of your AI inference workload is decode-stage-bound, latency-sensitive, and high-concurrency? Those are the workloads where OLIX's economics are most compelling.
- What is your current cost per million tokens at peak load, and what would you save if that cost fell 50-70%?
- Which of your AI workloads are long-running enough that a new inference platform's setup and migration cost would amortize over the deployment period?
The answers will tell you how much of your infrastructure strategy should be hedged against photonic AI compute becoming commercially available.
The Larger Bet
OLIX's $312 million Series B at $3.3 billion is one of the largest single investments in a chip company that has not yet shipped commercial silicon. The round reflects investor conviction that the combination of HBM economics, inference scaling requirements, and semiconductor physics limits makes photonic computing inevitable — the only question is which company gets there first at commercial scale.
James Dacombe, 25 years old at the time of the raise, is building infrastructure that, if it works at scale, could reset the economics of AI inference the way Nvidia's CUDA platform reset the economics of AI training in the late 2000s. CUDA was a software abstraction that made GPU hardware accessible to researchers who had never written graphics code — and that accessibility compounded into a 15-year lock-in that no competitor has successfully broken.
The OTPU is a hardware abstraction that eliminates the most expensive and supply-constrained component in AI inference infrastructure. If it works at scale, the lock-in it creates is not software but physics: no amount of engineering makes electrons behave like photons.
Takeaway: OLIX's $312 million photonic chip raise is the most important AI infrastructure bet since Etched's transformer ASIC round, and it attacks the inference bottleneck from a more fundamental direction. The HBM elimination is the headline, but the real story is the physics: photonic compute is not constrained by the silicon scaling limits that all GPU and ASIC alternatives ultimately inherit. The 2027 first deliveries will be the pivotal data point. Enterprise infrastructure teams with significant decode-stage inference workloads should be modeling photonic economics now — the procurement cycle for AI infrastructure runs 18-36 months, which means the analysis you run today shapes the decisions you make when OLIX's first chips hit the market.
Frequently Asked Questions
What is OLIX and what does it make?
OLIX is a London-based AI chip startup founded by 25-year-old James Dacombe. Formerly known as Flux Computing (rebranded January 2026), OLIX builds Optical Tensor Processing Units (OTPUs) — AI accelerators that use photons, or light particles, rather than electrical signals to perform the matrix multiplications at the heart of AI inference. The company's first commercial chip, the DX-1, specifically targets the decode stage of large language model inference, which is where the bottleneck typically lives in production systems. OLIX claims the DX-1 can deliver over 10,000 tokens per second per user while consuming significantly less power than equivalent GPU-based systems. The company raised $220 million in February 2026 at a $1 billion valuation, then closed a $312 million Series B in August 2026 at a $3.3 billion valuation. First commercial shipments are targeted for the second half of 2027.
Why does eliminating HBM matter for AI inference costs?
High-bandwidth memory (HBM) is the most expensive and supply-constrained component in Nvidia's AI data center GPUs. HBM is a specialized memory architecture that stacks DRAM chips vertically to achieve the extremely high memory bandwidth that large language models require — these models constantly shuffle billions of parameters between memory and compute during inference. HBM is expensive (adding thousands of dollars per GPU card), difficult to manufacture (TSMC and SK Hynix have limited production capacity), and its shortage has been a significant constraint on AI infrastructure buildout. OLIX's approach uses on-chip SRAM instead of HBM, keeping model weights closer to compute and reducing the memory bandwidth bottleneck by shortening the distance data travels. Eliminating HBM dependency means OLIX chips could be manufactured without the supply bottleneck that constrains Nvidia H100 and H200 production, and at significantly lower component cost per unit of inference throughput.
How does photonic computing work for AI inference?
Photonic computing uses light (photons) instead of electrical signals (electrons) to perform computations. For AI inference specifically, the key operation is the matrix-vector multiply-accumulate, which is what happens when an LLM processes each token. In conventional GPU chips, these operations happen in silicon transistors using electrical signals, which generate heat and consume substantial power. Photonic computing performs equivalent operations using light propagating through optical waveguides, which generates virtually no heat from the computation itself and can achieve very high bandwidth because photons travel at the speed of light. OLIX's OTPU architecture combines photonic compute (for the matrix multiply operations) with electronic SRAM (for weight storage) in a hybrid approach that captures the efficiency benefits of photonics while using proven memory technology. The practical output is higher tokens-per-second per watt than conventional GPU architectures — which is the unit economics of inference that matters most to AI infrastructure operators.
Who invested in OLIX's Series B and why does the UK Sovereign AI Fund matter?
OLIX's $312 million Series B was led by Fundomo, with participation from Arm (the chip architecture company owned by SoftBank), Hudson River Trading (the quantitative trading firm), and Reed Hastings, the co-founder and former CEO of Netflix. The participation of the UK government's Sovereign AI Fund — a £500 million state-backed initiative launched in April 2026 — is significant for several reasons. It signals that the UK government views OLIX as strategic national AI infrastructure, analogous to how countries view domestic semiconductor capacity. It also provides patient capital that doesn't require near-term returns, giving OLIX runway to complete chip development and reach H2 2027 first shipments. Arm's participation is strategically important: Arm designs the processor cores that underpin most data center chips, and its involvement suggests architectural integration planning between OLIX's optical compute and mainstream data center infrastructure. The combination of financial, strategic, and government investors is typical of deep-tech infrastructure bets, not software startups — which reflects the capital intensity and timeline of bringing a fundamentally new computing substrate to market.
What is the timeline for photonic AI chips reaching commercial scale?
OLIX targets first commercial chip shipments to customers in the second half of 2027, approximately 18 months from the August 2026 Series B close. The photonic AI chip market was valued at $3.14 billion in 2026 and is projected to reach $20 billion by 2035, implying a compound annual growth rate of roughly 20% across the decade. This growth trajectory assumes photonic chips can achieve the yield rates, manufacturing scale, and software ecosystem integration necessary to compete with GPU-based inference at commercial scale — none of which is guaranteed. The critical validation event for photonic AI inference economics will be the first large-scale customer deployments, likely with hyperscalers or large model providers who have both the capital to pilot new infrastructure and the inference workload scale where efficiency gains translate to material cost savings. OLIX is one of several photonic computing startups pursuing this market, alongside Lightmatter (US-based) and Salience Labs (UK), though the funding scale of OLIX's Series B is the largest in the sector to date.
How does OLIX compare to other Nvidia GPU alternatives like Etched and Cerebras?
OLIX, Etched, and Cerebras are all targeting the AI inference market with architectures that diverge from Nvidia's GPU approach, but they do so at different layers of the stack. Etched builds transformer-specific ASICs — application-specific integrated circuits that hardwire the transformer architecture in silicon, achieving extremely high performance for LLM inference at the cost of architectural rigidity. Etched's chips cannot be reprogrammed to run different model architectures; they are optimized exclusively for transformers. Cerebras built the largest single chip ever produced, the Wafer Scale Engine, eliminating chip-to-chip interconnect latency by putting an entire AI accelerator on a single silicon wafer. Cerebras has shipped working hardware and has public customer deployments. OLIX's photonic approach is more fundamental: it replaces the substrate of computation (electrons to photons), which theoretically enables efficiency improvements that are independent of semiconductor process node scaling. The trade-off is risk: photonics manufacturing is less mature than silicon CMOS, optical-electrical integration adds engineering complexity, and the software ecosystem for photonic accelerators is earlier than for silicon alternatives. The comparative advantage of photonic computing, if it achieves commercial scale, is that it sidesteps the physics limits approaching silicon transistor scaling — a longer-term moat than silicon optimization.